Sine Engineering is seeking a Physical Design Engineer to join the team building next-generation System-on-Chips (SoCs) from the ground up. The role involves driving the physical implementation flow from synthesis through place-and-route, timing closure, and GDSII sign-off. You will contribute to areas such as synthesis, floorplanning, timing closure, physical verification, DFT integration, low-power implementation, and package co-design. The position is open to all levels, from recent graduates to senior engineers with multiple tape-outs.

Responsibilities

Drive the physical implementation flow, from synthesis through place-and-route, timing closure, and GDSII sign-off.
Contribute to one or more of the following areas:
Synthesis and constraint development (SDC), including handoff between front-end and back-end teams.
Floorplanning, power planning, placement, clock tree synthesis, and routing for SoC blocks and full-chip integration.
Timing closure across PVT corners and operating modes, including STA, ECO planning, and sign-off.
Physical verification, including DRC, LVS, ERC, antenna checks, and electromigration/IR-drop analysis.
DFT integration and implementation, including scan insertion, compression, MBIST, boundary scan, and ownership of test pattern generation flows.
Low-power implementation, including UPF/CPF co-design flows, power domains, level shifters, isolation, and retention strategies.
Package definition and co-design, including pinout planning, bump/ball assignment, package-aware signal and power integrity, and collaboration with package and board teams.
Tape-out preparation and sign-off, including GDSII generation, foundry deliverables, and DRC/LVS-clean handoff.

Requirements

Background in SoC physical design, ranging from recent graduates with strong fundamentals and relevant project experience to senior engineers with multiple successful tape-outs.
Working knowledge of the complete RTL-to-GDSII flow (appropriate to experience level), including synthesis, place-and-route, STA, and physical verification.
Familiarity with industry-standard EDA tools such as Synopsys Design Compiler, Fusion Compiler, IC Compiler, Cadence Genus, Innovus, Siemens Calibre, or equivalent solutions.
Solid understanding of timing analysis, CDC, low-power design methodologies, and design-for-test concepts.
Scripting proficiency in Tcl, Python, or Perl for flow automation and analysis.
Strong debugging skills and a structured approach to resolving complex implementation challenges.
A proactive attitude, strong ownership mindset, and eagerness to learn and grow with the team.

Nice to have

Experience with package definition, pinout optimization, and package/PCB co-design.
Experience with mixed-signal or RF SoC implementation and analog-to-digital integration.
Knowledge of signal integrity, power integrity, and electromigration analysis.
Experience with hierarchical implementation methodologies and large-block partitioning.

Benefits

Paid time off in accordance with Finnish labor legislation.
Lunch Benefit: Daily lunch allowance up to the tax-free limit.
Sport & Culture Benefit: Annual budget for gym memberships, sports activities, cultural events, and hobbies.
Wellbeing Allowance: Additional support for massages, mental health services, and other wellness-related activities.
Extended Occupational Healthcare: Enhanced coverage including GP visits, specialist care, mental health support, and partial dental coverage.
24/7 Accident Insurance: Coverage during both work and personal time.
Business Travel Insurance: Comprehensive coverage for work-related travel.
Company Phone & Subscription: Provided as an employee benefit.
Office Perks: Complimentary coffee, snacks, fruit, and other office amenities.
No-Crunch Culture: No systematic overtime. Any overtime is compensated in accordance with company policy.
Meeting-Light Culture: Protected focus time with minimal unnecessary meetings.
Low-Hierarchy Environment: High autonomy, strong ownership, and zero micromanagement.
High-End Equipment: Premium laptop, monitor, and peripherals.
Lab & Gadget Budget: Annual budget for hardware, tools, books, and learning materials.
Hackathons & Offsites: Regular events focused on innovation, experimentation, and technology.
Full reimbursement of business travel expenses, including transportation and accommodation.
Daily per diem allowances based on the maximum tax-free rates published by the Finnish Tax Administration (Vero).